베릴로그,Verilog

Difference between r1.2 and the current

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[[모듈,module]]
#noindex
##====베릴로그,Verilog =,Verilog 베릴로그 Verilog
Terms
module [[모듈,module]] 
a block of code that performs specific function
port
input port
output port
module 선언 시 처음에 input/outport port list 나열.

MKL
HDL [[하드웨어기술언어,hardware_description_language,HDL]]
EDA electronic design automation 전자설계자동화 ? Ggl:"electronic design automation"
[[digital_design]]
[[회로,circuit]]
[[시뮬레이션,simulation]]
 
<<tableofcontents>>
 
= Videos =
 
Verilog for Beginners - YouTube
https://www.youtube.com/playlist?list=PL9K1-gZiaFsMhcfMt0mdIgzhyx3VOJlI3
----
[[하드웨어기술언어,hardware_description_language,HDL]]
[[VG:베릴로그,Verilog]]
YouTube:"Verilog 강의"
----
Hardware Description Language Programming (Verilog) - YouTube
Derek Johnston
https://www.youtube.com/playlist?list=PLTFN8e-Y3kpEhLKNox-tRNJ9eNFxZopA0
----
Introduction to Verilog HDL using Free Software Icarus, GTKWave, and VS Code - YouTube
https://www.youtube.com/watch?v=vN1wzM0NO4c

Verilog modeling styles
{
gate-level modeling
{{{
and a1(o,a,b);
or or1(o,c,d);
}}}
dataflow modeling
{{{
assign Y=((!A)&&B)||(!C)
}}}
behavioral modeling
{{{
primitive pName(D,A,B,C);
output D;
input A,B,C;
table
0 0 0 : 1
0 0 1 : 0
0 1 0 : 1
0 1 1 : 1
1 0 0 : 0
endtable
endprimitive
}}}

모듈선언 간소화. old version:
{{{
module ModuleName(X,Y,A,B)
output X,Y;
input A,B;
…
endmodule
}}}
2005 version:
{{{
module ModuleName(output X,Y, input A,B)
…
endmodule
}}}
}
= Twins =
https://ko.wikipedia.org/wiki/베릴로그

https://en.wikipedia.org/wiki/Verilog
 
----
[[VG:베릴로그,Verilog]]
 
= Examples =
excerpts from Mano
 
E=(A+B)C
{{{
module or_and( output E, input A, B, C );
wire D;
assign D = A || B; // logical or
assign E = C && D; // logical and
endmodule
}}}
 
----
[[멀티플렉서,multiplexer]] example from https://youtu.be/9SbI38MMN7Y?t=2267 - see there for diagram
{{{
module multiplexer (D0, D1, S, Z);
output Z;
input D0, D1, S; // S는 화면에 빠졌는데 있어야 함
wire temp0, temp1;
 
not (Sbar, S);
and (temp0, DO, Sbar);
and (temp1, D1, S);
or (Z, temp0, temp1);
endmodule
}}}
 
----
ex. from https://www.youtube.com/watch?v=2IReMT_zjK8
2-to-1 [[멀티플렉서,multiplexer]]
https://i.imgur.com/Z9qpWjL.png
https://i.imgur.com/0KqnQ4d.png
gate level
{{{
module multiplex_gatelevel(A,B,X,out1);
input A, B, X;
output out1;
wire not_x;
wire out_and1, out_and2;
not not1(not_X, X);
and and1(out_and1, not_X, A);
and and2(out_and2, X, B);
or or1(out1, out_and1, out_and2);
endmodule
}}}
dataflow level
{{{
module multiplex_datalevel(A,B,X,out1);
input A, B, X;
output out1;
assign out1 = ((~X&A)&A)|(B&X);
endmodule
}}}
behavioral level
{{{
module multiplex_behavior(A,B,X,out1);
input A, B, X;
output reg out1;
always@(*)
begin
if(X==0)
out1 = A;
else
out1 = B;
end
endmodule
}}}
----
half_adder example from https://youtu.be/IREjtgG33hQ?t=131
{{{
module HalfAdd_Behave2 (a,b,c,s);
input a,b;
output c;
output reg s; // <- output from always block goes to registers
always // procedural statements must be inside 'always' block
@(a,b) // @(...) : sensitivity list
// 'always @(a,b)' means the always block is executed whenever a or b (or both) changes. always @(*) 또는 @*로 쓰고 컴파일러가 알아서 어떤 신호를 고려하게 할 지 하는 것도 가능.
if (a != b)
s = 1;
else
s = 0;
assign c = a&b; // <- output of continuous assignment goes to net
endmodule // HalfAdd_Behave2
}}}


Terms
module 모듈,module
a block of code that performs specific function
port
input port
output port
module 선언 시 처음에 input/outport port list 나열.


MKL
HDL 하드웨어기술언어,hardware_description_language,HDL
EDA electronic design automation 전자설계자동화 ? Ggl:electronic design automation
digital_design
회로,circuit
시뮬레이션,simulation



[edit]

1. Videos


Hardware Description Language Programming (Verilog) - YouTube
Derek Johnston
https://www.youtube.com/playlist?list=PLTFN8e-Y3kpEhLKNox-tRNJ9eNFxZopA0
Introduction to Verilog HDL using Free Software Icarus, GTKWave, and VS Code - YouTube
https://www.youtube.com/watch?v=vN1wzM0NO4c

Verilog modeling styles
{
gate-level modeling
and a1(o,a,b);
or  or1(o,c,d);
dataflow modeling
assign Y=((!A)&&B)||(!C)
behavioral modeling
primitive pName(D,A,B,C);
  output D;
  input A,B,C;
  table
    0 0 0 : 1
    0 0 1 : 0
    0 1 0 : 1
    0 1 1 : 1
    1 0 0 : 0
  endtable
endprimitive

모듈선언 간소화. old version:
module ModuleName(X,Y,A,B)
output X,Y;
input A,B;
…
endmodule
2005 version:
module ModuleName(output X,Y, input A,B)
…
endmodule
}
[edit]

2. Twins

[edit]

3. Examples

excerpts from Mano

E=(A+B)C
module or_and( output E, input A, B, C );
wire D;
assign D = A || B; // logical or
assign E = C && D; // logical and
endmodule

멀티플렉서,multiplexer example from https://youtu.be/9SbI38MMN7Y?t=2267 - see there for diagram
module multiplexer (D0, D1, S, Z);
output Z;
input D0, D1, S; // S는 화면에 빠졌는데 있어야 함
wire temp0, temp1;

not (Sbar, S);
and (temp0, DO, Sbar);
and (temp1, D1, S);
or (Z, temp0, temp1);
endmodule

ex. from https://www.youtube.com/watch?v=2IReMT_zjK8
2-to-1 멀티플렉서,multiplexer
https://i.imgur.com/Z9qpWjL.png

https://i.imgur.com/0KqnQ4d.png

gate level
module multiplex_gatelevel(A,B,X,out1);
input A, B, X;
output out1;
wire not_x;
wire out_and1, out_and2;
not not1(not_X, X);
and and1(out_and1, not_X, A);
and and2(out_and2, X, B);
or or1(out1, out_and1, out_and2);
endmodule
dataflow level
module multiplex_datalevel(A,B,X,out1);
input A, B, X;
output out1;
assign out1 = ((~X&A)&A)|(B&X);
endmodule
behavioral level
module multiplex_behavior(A,B,X,out1);
input A, B, X;
output reg out1;
always@(*)
begin
if(X==0)
out1 = A;
else
out1 = B;
end
endmodule
half_adder example from https://youtu.be/IREjtgG33hQ?t=131
module HalfAdd_Behave2 (a,b,c,s);
input a,b;
output c;
output reg s; // <- output from always block goes to registers
always //  procedural statements must be inside 'always' block
@(a,b) // @(...) : sensitivity list
// 'always @(a,b)' means the always block is executed whenever a or b (or both) changes. always @(*) 또는 @*로 쓰고 컴파일러가 알아서 어떤 신호를 고려하게 할 지 하는 것도 가능.
 if (a != b)
  s = 1;
 else
  s = 0;
 assign c = a&b; // <- output of continuous assignment goes to net
endmodule // HalfAdd_Behave2
베릴로그,Verilog Modified on 7:16 pm, August 21, 2024.
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