하드웨어기술언어,hardware_description_language,HDL

Difference between r1.1 and the current

@@ -6,3 +6,27 @@


[[하드웨어,hardware]] [[기술언어,description_language]]
 
Sub:
[[베릴로그,Verilog]]
{
[[베릴로그,Verilog]]
https://en.wikipedia.org/wiki/Verilog
}
SystemVerilog
VHDL
 
----
MKL
하드웨어XX언어
hardware_verification_language
{
hardware verification language
 
Sub:
OpenVera
{
https://en.wikipedia.org/wiki/OpenVera
}//OpenVera ... Ggl:OpenVera Naver:OpenVera
 
}//hardware verification language ... Ggl:"hardware verification language" Naver:"hardware verification language"








MKL
하드웨어XX언어
hardware_verification_language
{
hardware verification language


}//hardware verification language ... Ggl:hardware verification language Naver:hardware verification language